[Bug] How to use auto_scheduler to generate SVE code

[yohuna77777]

Hello, I am currently using auto_scheduler to automatically tune a naive gemm operator. However, after the tuning is completed, I checked the corresponding assembly code and found that the registers related to the SVE instruction set were not used, but the NEON instruction set was used(The target is set to: "llvm -mtriple=aarch64-gnu-linux -mattr=+sve"). Does auto_scheduler not support the generation of SVE code? Looking forward to your reply!

[yohuna77777]

In fact, I wrote a naive gemm, and after setting the target, the compiled code still did not use the sve instruction set. What's going on? The code is as follows:
`
import tvm
import tvm.testing
from tvm import te
from tvm.script import tir as TIR
import re
import os
import ctypes
import pytest

from tvm.target.codegen import llvm_version_major

target = "llvm -mtriple=aarch64-linux-gnu -mattr=+sve"

#m = te.var("m")
#A = te.placeholder(m, dtype="float32", name="A")
#B = te.placeholder(m, dtype="float32", name="B")
#C = te.compute((m), lambda i: A[i] * B[i], name="C")
M = 1024
N = 1024
K = 1024
A = te.placeholder((M, K), name="A", dtype="float32")
B = te.placeholder((K, N), name="B", dtype="float32")

k = te.reduce_axis((0, K), name="k")
C = te.compute(
(M, N),
lambda i, j: te.sum(A[i, k] * B[k, j], axis=k),
name="C",
attrs={"layout_free_placeholders": [B]}, # enable automatic layout transform for tensor B
)
s = te.create_schedule([C.op])

f = tvm.build(s, [A, B, C], target)

assembly = f.get_source("asm")
print(assembly)
`