GitHub - MiguelSMoreira/VHDL-Scalar-Processor: VHDL implementation of a scalar processor with a 16-bit instruction hardwired control unit, 32-bit processing unit and a custom microprogramed instruction decoder and branch control unit

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VHDL implementation of a scalar processor with a 16-bit instruction hardwired control unit, 32-bit processing unit and a custom microprogramed instruction decoder and branch control unit

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
.DS_Store		.DS_Store
.gitattributes		.gitattributes
.lso		.lso
.schlog		.schlog
CicloUnico3.ise		CicloUnico3.ise
CicloUnico3.restore		CicloUnico3.restore
MUX16_32.sch		MUX16_32.sch
MUX16_32.sym		MUX16_32.sym
MUX2_32.sch		MUX2_32.sch
MUX2_32.sym		MUX2_32.sym
PCReg.sym		PCReg.sym
PCReg.vhd		PCReg.vhd
Processador2012.sch		Processador2012.sch
RES32AR.sym		RES32AR.sym
RES32AR.vhd		RES32AR.vhd
RES4AR.vhd		RES4AR.vhd
StateRegister.sym		StateRegister.sym
TBZ.sch		TBZ.sch
TBZ.sym		TBZ.sym
UA.sch		UA.sch
UA.sym		UA.sym
UArith.sch		UArith.sch
UArith.sym		UArith.sym
UCS.sch		UCS.sch
UCS.sym		UCS.sym
UDI.sch		UDI.sch
UDI.sym		UDI.sym
UF.sch		UF.sch
UF.sym		UF.sym
ULogic.sch		ULogic.sch
ULogic.sym		ULogic.sym
UShift.sch		UShift.sch
UShift.sym		UShift.sym
adder32.sch		adder32.sch
adder32.sym		adder32.sym
data_mem.sym		data_mem.sym
data_mem.vhd		data_mem.vhd
idecoder_mem.sym		idecoder_mem.sym
idecoder_mem.vhd		idecoder_mem.vhd
inst_mem.sym		inst_mem.sym
inst_mem.vhd		inst_mem.vhd
isim.log		isim.log
t.ant		t.ant

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VHDL implementation of a scalar processor with a 16-bit instruction hardwired control unit, 32-bit processing unit and a custom microprogramed instruction decoder and branch control unit

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