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Add DHCEN primitive. #261

Merged
merged 9 commits into from
Sep 12, 2024
Merged

Add DHCEN primitive. #261

merged 9 commits into from
Sep 12, 2024

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yrabbit
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@yrabbit yrabbit commented Jul 20, 2024

Added parts necessary to generate chip databases with DHCEN support for all supported boards. The packing was made with the necessary fuses set.

DHCEN is provided as a wire to disable the input MUXes of HCLK, effectively turning off everything that is "beyond" those MUXes.

Most of the work happens in the nextpnr part.

Added parts necessary to generate chip databases with DHCEN support for
all supported boards. The packing was made with the necessary fuses set.

DHCEN is provided as a wire to disable the input MUXes of HCLK,
effectively turning off everything that is "beyond" those MUXes.

Most of the work happens in the nextpnr part.

Signed-off-by: YRabbit <[email protected]>
@yrabbit
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yrabbit commented Jul 20, 2024

For now as a draft for two reasons:

  • Tangnano9k has his own ideas about how DHCEN works.
  • There are no examples. Simple things like ODDR & Co have a dual clock input - HCLK and regular clock wires and coming up with a mechanism to ensure HCLK is engaged so that you can use DHCEN doesn't make much sense when there is CLKDIV, so wait for CLKDIV, after which there will be examples.

Added an example of using DHCEN. It uses CLKDIV and CLKDIV2 so it will
work on boards that support these primitives.

The Tangnano9k board is currently being investigated because there are
some unknowns there.

Signed-off-by: YRabbit <[email protected]>
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yrabbit commented Jul 21, 2024

In the example, DHCEN controls all networks at once depending on the state of the button. In the unpressed position, all HCLK networks are disabled (in fact, all used input MUXes are disabled) and only the first LED flashes. When pressed, the second LED begins to show the operation of CLKDIV/CLKDIV2.

pr20.mp4
tn20.mp4

An interesting mechanism for transmitting signals between HCLK banks (or
otherwise parties) has been discovered.

We have two points, each of which can receive a signal from any HCLK and
transmit it to any other HCLK.

No complex signals can be transmitted here - the input lines are limited
by HCLK_INx, and we also need to see which components can use the output
from these two points, but so far the tests are encouraging: it is
possible to transmit a signal from the clock pin from one side of the
chip to the opposite and feed CLKDIV2 there using just a couple wires!

Signed-off-by: YRabbit <[email protected]>
Signed-off-by: YRabbit <[email protected]>
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Seems like this is waiting for YosysHQ/nextpnr#1349 ?

@yrabbit yrabbit marked this pull request as ready for review September 11, 2024 09:38
@yrabbit yrabbit merged commit 4f87247 into YosysHQ:master Sep 12, 2024
12 of 14 checks passed
@yrabbit yrabbit deleted the dhcen-ctl branch September 12, 2024 03:01
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2 participants